About Us

Led by Director Shailesh Vasekar, our team brings deep knowledge in functional verification using advance verification methodologies such as VERA, VMM, OVM, UVM, and SystemVerilog.

Full-Cycle Verification

  • • We have Worked on all stages of functional verification from defining verification strategy, testplan development, defining functional coverage goals.
  • • Development of full verification testbench & environment components like driver, monitor, reference model, scoreboard, sequences, testscases.
  • • Bug reporting, regression runs and coverage closure.
  • • Block level, cluster or subsystem level and SOC level verification.
Advanced Methodologies
  • • Developing testbench from basics.
  • • Sequence layering, virtual sequences.
  • • Register Abstraction Layer based register verification.
  • • Applied constrained random techniques to find early bugs.
  • • Exposure to formal equivalence technique of Jasper.
  • • Worked on GLS.