Unmatched Verification Rigor
At neurotech, our IP, Subsystem, and SOC Design Verification team treats every project with mission-critical importance. We build highly scalable, constrained-random verification environments utilizing the Universal Verification Methodology (UVM) and SystemVerilog. Our approach ensures that every possible state, interaction, and corner case is thoroughly exercised.
Our Capabilities
- IP-Level Verification: Creating standalone testbenches for complex standard IPs (PCIe, Ethernet, DDR, CXL) and custom logic blocks.
- Sub-System Verification: Verifying the complex interactions between multiple IPs, DMA controllers, and memory sub-systems.
- SoC-Level Verification: Full-chip integration testing, boot ROM sequence validation, and hardware-software co-verification using C/C++ tests running on embedded processors (ARM, RISC-V).
- Formal Verification: Deploying mathematical proofs using tools like JasperGold to mathematically guarantee the absence of deadlocks, livelocks, and protocol violations.
- Gate-Level Simulation (GLS): Running SDF-annotated netlist simulations to verify timing and power-aware logic (UPF).
ARM SoC Verification Expertise
We offer world-class expertise in validating ARM-based systems, including full testbench development, software-driven verification, PCR (Power, Clock, Reset) validation, and complete power analysis utilizing UPF.
ARM Based SoC Architecture
Comprehensive verification covering entire ARM-based ecosystems, from multi-core clusters to complex interconnect fabrics.
- A-Class Based Cluster (ARMv8/v9 Architecture): Verification of Big, Medium, and Little core topologies.
- M-Class Based Subsystem (Security/PCR): Validating M85/M55 cores, AON subsystems, Interconnect/PLL power-up, and Init Subsystems.
- Fabric & Interconnects: Verification of Coherent (CCI/CMN) and Non-Coherent (NI-Tower) interconnects, along with memory and GIC interrupt maps.
- Peripheral Subsystems: Comprehensive testing of LSIO, LPDDR, and HSIO subsystems.
- Debug Components: Validating CoreSight (CSS600) and other debug infrastructure elements.
ARM Based SoC: C + UVM Testbench Design
We develop advanced testbenches that bridge hardware verification with embedded software tests, accelerating validation cycles.
- ASM Code for A/M Class Processor: Writing core assembly sequences to initialize hardware registers, cache subsystems, and memory managers.
- ARM RVDS Compiler: Compiling low-level firmware and diagnostic tests using industrial ARM Toolchains.
- Scatter File Routing: Configuring custom linker scatter files to position boot code, stacks, and heaps dynamically in internal memory arrays.
- Hex Code Preloading: Scripted mechanisms to pre-load compiled test code directly into system RAM/Flash memory models at simulation startup.
- Reset & Clock to CPU: Integrating core system clocks and complex CPU reset state machines into UVM environments.
- CPU Boot & C-Test End: Verification environments that track code execution milestones. Hardware tests are gracefully terminated via coordinate C + UVM objection drops when software diagnostics finish.
ARM Based SoC: Bringup, Software & Boot Flow
Full-chip integration testing from the initial hardware reset vector to running bare-metal libraries.
- Bringup and CPU Boot: Ensuring correct vector fetching, exception table loading, and state transition validation.
- Software Library Development: Creating customized, highly optimized driver libraries to interact with core hardware modules (registers, DMA, GPIOs).
- Boot Flow Verification: Complete validation of boot paths, including cold boot, warm boot, software resets, and recovery loops.
ARM Based SoC: PCR Verification
Verifying the critical power, clock, and reset controllers that govern energy-efficient architectures.
- Clock Domain Verification: Safe clock domain crossing (CDC) checks for registers running on asynchronous clock trees.
- Clock Gating/Ungating: Dynamic gating verification to prevent glitches while keeping power draw to a minimum.
- Q-Channel / Q-Active Contributor Checks: Verification of low-power handshake protocols for clock gating and power domain shutoff.
Power & UPF (Unified Power Format) Verification
Functional verification of power management states and power intent assertions.
- Power Verification Functional Scenarios: Multi-domain power transitions:
ON → OFF / FUNC / FULL_RET (Full Retention) → WARM_RESET.
- PST (Power State Table) Verification: Mathematically proving the correctness of all legal power state combinations across the design.
- Isolation & Clamp Assertions: Verifying clamp cells force output signals to correct values when domain is powered down.
- QPA (Query Power Analyst) Assertions: Assertions to check integrity of power domain boundaries.
- Clock Gating + Power Scenarios: Comprehensive checks of clock gates during power-down and power-up phases to avoid state corruption.